1. Field of the Invention
This invention relates to multiprocessor systems and, more particularly, to interrupt controllers and interprocessor communication mechanisms for use in such systems.
2. History of the Prior Art
The personal computer industry is a vibrant and growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful personal computers. In order to meet this demand, computer designers have used various methods to increase the speed with which personal computers can process instructions. Historically, the personal computer has developed as a system utilizing a single microprocessor to handle all instruction execution. The microprocessor is the key working unit or "brains" of the personal computer, and its task is to handle all of the instructions that programs give it in the form of computer software.
One method that is being used to increase the speed of the personal computer is the incorporation of multiple microprocessors operating in parallel into a computer system. With the use of multiple processors, or multiprocessing, each microprocessor can be working on a different task at the same time. Systems that incorporate multiprocessing generally use standard microprocessors that operate off of a common bus and share a common memory. The use of multiprocessing has generally increased computer performance, but it has also introduced new design considerations that were not found in a single processor environment.
One consideration that arises in multiprocessing is how to allow the processors to communicate with each other. Communication between the processors in a multiprocessor system is generally necessary for the proper functionality of the system. One method that has been used for multiprocessor communication includes the use of input/output (I/O) registers which enable the processors to pass messages back and forth. The use of I/O registers, however, has conventionally required an address decode using a large number of address and control signals. Putting the registers on the local bus to minimize time spent by the processors on interprocessor communication leads to obstructive loading effects. Using other address lines, on the other hand, generally leads to increased pin count of connectors used with cards containing microprocessors.
Another consideration that arises in multiprocessing is how to control the operation of all of the processors. In some systems, a supervisory processor is used to control the operation of all other processors. However, this approach suffers insofar as it involves significant hardware and processing overhead.
An alternative approach is to eliminate the supervisory processor and have each processing unit capable of autonomous operation. Supervisory control is thereby accomplished within an operating system common to all of the processors. This approach requires a network of interprocessor communications such that the activities of each processor may be controlled by the operating system and synchronized, when required, with activities of other processors.
Prior art multiprocessor systems have only limited interprocessor communication capabilities. Most prior art systems employ a shared memory through which data may be exchanged by memory operations such as a read-modify-write sequence. Control functions may be effectuated in a similar manner by causing one processor to write to a control word location in shared memory, which location is subsequently read by another processor. Local copies of the shared memory space (or portions thereof) may be maintained by the individual processors. For example, the HEP processor of Denelcor utilizes a form of shared memory communications in which each shared memory location includes a lock bit for controlling access.
Shared memory multiprocessors typically communicate control information via messages sent through shared communication areas in memory. When one processor wishes to send a message to another, it first obtains exclusive access to a predetermined communication area. Exclusive access is obtained either by prior allocation of communication areas or by the use of locks provided by the operating system and implemented via indivisible operation provided by the processor's instruction set (e.g., test-and-set). Once the message has been written to the communication area, the sending processor uses a second mechanism to inform the receiving processor that data has been sent. In some cases, the message simply is left in the communication area, to be read by the receiving processor when it does a periodic poll of its communication areas. In other cases, the sending processor sends a message interrupt to the receiving processor via the bus interconnecting the processors. The receiving processor, upon recognizing the interrupt, processes the incoming message. Message and message interrupt sending typically are operating system functions.
Based upon the foregoing, those skilled in the art should understand and appreciate that the limited interprocessor communication capabilities of prior art multiprocessor systems present a multitude of problems. One problem is the fact that there is not a direct and efficient system that allows vectored interrupts to be routed to an arbitrary processor. A second, underlying problem is the fact that non-processor elements have not been well incorporated into interprocessor communication and multiprocessor interrupt control operations, to facilitate and enhance them. Heretofore, elements such as I/O bridges have been considered to be merely complicating factors with respect to communications and interrupt control in multiprocessing systems, rather than as presenting opportunities to speed those operations.